01 The Team
Researchers pushing the boundaries of hardware security
Advancing hardware security through |
Researchers pushing the boundaries of hardware security
Our focus areas at the intersection of ML and hardware
Applying RL agents to automate and optimize electronic design automation workflows, from floorplanning to place-and-route.
Leveraging large language models to generate, verify, and debug RTL code, improving designer productivity and design quality.
Detecting hardware Trojans, side-channel vulnerabilities, and ensuring silicon integrity through ML-driven analysis.
Insights and deep dives into hardware security and chip design
An overview of the ASIC design flow, from specification and RTL design through synthesis, place-and-route, verification, and tape-out.
An introduction to hardware security challenges including side-channel attacks, fault injection, IP protection, and design-for-trust.
A deep dive into hardware Trojans — malicious modifications to integrated circuits that can compromise security.
How artificial intelligence and machine learning are transforming chip design, from ML-driven floorplanning to LLM-based RTL generation.
Upcoming conference paper submission deadlines
Tools, frameworks, and open-source contributions
A reinforcement learning framework for security-aware electronic design automation, integrating threat models into the optimization loop.
An LLM-powered toolkit for generating, analyzing, and debugging Register Transfer Level hardware descriptions with built-in security checks.
Interested in collaborating or joining the lab? We'd love to hear from you.