As the semiconductor supply chain becomes increasingly globalized and complex, hardware security has emerged as a critical concern. Unlike software vulnerabilities that can be patched, hardware flaws are permanent once a chip is fabricated, making security a first-class design consideration.
The Hardware Threat Landscape
Hardware faces a diverse set of threats across its lifecycle:
- Hardware Trojans: Malicious modifications inserted during design or fabrication that can leak data, cause denial-of-service, or create backdoors
- Side-Channel Attacks: Exploiting physical emissions (power, electromagnetic, timing) to extract secret keys from cryptographic implementations
- Fault Injection: Deliberately inducing faults via voltage glitching, laser, or electromagnetic pulses to bypass security mechanisms
- Reverse Engineering: Extracting the design or proprietary IP from a manufactured chip through delayering and imaging
- Counterfeiting: Producing unauthorized copies, remarking, or recycling used chips as new
Design-for-Trust
Design-for-Trust (DfT) encompasses techniques embedded during the design phase to enhance a chip's resilience against attacks:
Logic Locking
Logic locking inserts key-controlled gates into the design netlist. Without the correct key, the chip produces incorrect outputs, protecting the IP from untrusted foundries. Modern techniques like SFLL (Stripped Functionality Logic Locking) are designed to resist SAT-based attacks.
Physically Unclonable Functions (PUFs)
PUFs exploit inherent manufacturing variations to generate unique, device-specific identifiers. They serve as silicon fingerprints for authentication without requiring secure key storage.
Camouflaging
Layout camouflaging makes standard cells appear identical under microscopy, preventing reverse engineering from extracting the netlist from chip images.
Side-Channel Countermeasures
Defending against side-channel attacks requires both algorithmic and implementation-level protections:
- Masking: Splitting sensitive values into random shares so that any single share reveals no information
- Constant-Time Implementations: Ensuring execution time is independent of secret data
- Power Balancing: Equalizing power consumption across different operations to reduce power side-channel leakage
- Noise Injection: Adding random activity to obscure the signal an attacker is trying to measure
Our Research: At ASEEC, we are developing ML-driven approaches to automatically detect side-channel vulnerabilities in RTL designs, enabling designers to identify and fix leakage points before fabrication.
ML for Hardware Security
Machine learning is transforming hardware security in several ways:
- Trojan Detection: GNN-based classifiers that analyze gate-level netlists to identify suspicious circuit structures
- Side-Channel Analysis: Deep learning models that can break cryptographic implementations with fewer traces than traditional statistical methods
- Anomaly Detection: Identifying counterfeit or tampered chips through statistical analysis of test data
- Automated Verification: LLM-assisted security property checking and assertion generation
The Path Forward
Hardware security requires a holistic approach spanning design, fabrication, testing, and deployment. As chips become more complex and supply chains more distributed, the role of AI-driven security tools will only grow. Our group is committed to building the next generation of automated hardware security solutions.